The present invention relates to a nonvolatile semiconductor memory device using a diode as an access element.
Recently, Magnetic Random Access Memory (MRAM) has drawn attention as a next-generation semiconductor memory device in place of Dynamic Random Access Memory (DRAM) or Statistic Random Access Memory (SRAM). This MRAM receives attention as such a nonvolatile semiconductor memory device in that, in theory, a high speed operation comparable to SRAM and a high integration comparable to DRAM can be realized at the same time, and data can be rewritten unlimitedly with low power consumption.
In MRAM, Tunneling Magnetoresistive (TMR) element has been proposed as a memory element storing data. This TMR element includes a Magnetic Tunneling Junction (MTJ) made of two ferromagnetic layers and a thin tunnel insulator layer therebetween, and an antiferromagnetic layer in contact with one of the ferromagnetic layers.
Predominantly, that one of ferromagnetic layers which is in contact with the antiferromagnetic layer is exchange coupled to the antiferromagnetic layer and has a fixed magnetic moment. This ferromagnetic layer is called a fixed layer. On the other hand, that one of ferromagnetic layers which is not in contact with the antiferromagnetic layer has its magnetization direction changed easily by externally applying a magnetic field. These characteristics are utilized to rewrite data into a memory cell. The ferromagnetic layer having a magnetization direction inverted by an external magnetic field is called a free layer.
In the TMR element having the structure described above, the magnetization direction of the free layer with respect to the magnetization direction of the fixed layer is controlled in parallel/antiparallel to vary the resistance value because of the tunneling magneto-resistance effect. In MRAM, this tunneling magneto-resistance effect is utilized to read out data.
Generally, in a nonvolatile semiconductor memory device using TMR elements, memory cells are arranged in rows and columns. The Reference concerning a nonvolatile semiconductor memory device having memory cells arranged in rows and columns includes U.S. Pat. No. 5,640,343. In the nonvolatile semiconductor memory device disclosed in this publication, in a manner corresponding to memory cells arranged in rows and columns, a bit line as a first conductive line is arranged for each column and a word line as a second conductive line is arranged for each row. In an intersection region with a bit line and a word line, a memory cell formed of a TMR element and a diode connected in series is arranged. Here, a diode connected in series to a TMR element is an access diode that functions as an access element to a memory cell.
In the nonvolatile semiconductor memory device having the structure described above, a composite magnetic field formed of magnetic fields in two directions is created by passing current through a bit line and a word line that are selected from a plurality of word lines and bit lines crossing each other. This composite magnetic field is used to rewrite the magnetization direction of the free layer.
On the other hand, in reading data, a word line corresponding to a selected memory cell is set to a low voltage (for example a ground voltage VSS) state. At this point, a bit line is precharged to a high voltage (for example a power supply voltage VCC) state to allow a diode to be rendered conductive and to allow a sense current to flow in the selected MTJ. The data can thus be read. It is noted that in the non-selected memory cell, since the word line is set to a high voltage state to maintain the corresponding diode in a non-conductive state, a sense current does not flow in the non-selected MTJ.
As described above, a so-called one-MTJ+ one-diode type nonvolatile semiconductor memory device having a memory cell formed of one TMR element and one access diode allows the memory cell array area to be smaller than a so-called one-MTJ+ one-transistor type nonvolatile semiconductor memory device using a transistor as an access element, whereby the integration may be improved drastically. Therefore, the nonvolatile semiconductor memory device of one-MTJ+ one-diode type has been developed intensively.
When this one-MTJ+ one-diode type nonvolatile semiconductor memory device is actually formed on a semiconductor substrate, the structural restriction and the process restriction impose limitations on the freedom of its design. Among others, some structures as illustrated below have been proposed.
A first structure has a word line of a metal material formed on a silicon substrate, an n-type silicon layer and a p-type silicon layer successively deposited on the word line, a TMR element formed thereon, and a bit line of a metal material deposited thereon (see for example FIG. 1C of U.S. Pat. No. 5,640,343). In this structure, the n-type silicon layer and the p-type silicon layer form an access diode and an pn junction is formed at their interface. It is noted that a polysilicon layer or an amorphous silicon layer is used as the n-type silicon layer and the p-type silicon layer.
A second structure has a p-type diffusion region and an n-type diffusion region formed on a main surface of a p-type silicon substrate, a TMR element formed on the p-type diffusion region, and a bit line of a metal material deposited thereon (see for example FIGS. 10A-10C of U.S. Pat. No. 5,640,343). In this structure, a word line is formed with the n-type diffusion region, an access diode is formed of the p-type diffusion region and the n-type diffusion region, and a pn junction is formed at their interface.
A third structure has a word line of a metal material formed on a silicon substrate, a TMR element formed on the word line, an n-type silicon layer doped with phosphorus (P) formed thereon, an aluminum layer deposited thereon, and a bit line formed thereon (see for example FIG. 8 of Japanese Patent Laying-Open No. 2000-196030). In this structure, the n-type silicon layer doped with phosphorus and the aluminum layer form a shot key diode. It is noted that a polysilicon layer or an amorphous silicon layer is used as the n-type silicon layer doped with phosphorus.
Although, in the foregoing, MRAM using a magneto-resistance effect element as a memory element applied to a memory cell has been described, a nonvolatile semiconductor memory device having a capacitive memory element applied to a memory cell is known as an alternative nonvolatile semiconductor memory device (see for example FIG. 4 of Japanese Patent Laying-Open No. 7-176772). The nonvolatile semiconductor memory device described in Japanese Patent Laying-Open No. 7-176772 uses an anti-fuse that is a kind of capacitive memory elements, as a memory element, and further uses a diode connected in series to this anti-fuse, as an access element.
In the nonvolatile semiconductor memory device described above, the electric characteristics of the diode employed as an access element is extremely important. For example, in MRAM, the value of the read current in reading data is decided by the relation between a potential difference between a word line and bit line and an resistance value of an access diode and a TMR element. Therefore, the variations in internal resistance of the diode prevents information stored in the TMR element from being read out correctly. The reverse direction characteristics of the individual diode is also important, and variations in leak current may cause an error. In other words, in order to implement a nonvolatile semiconductor memory device using a diode as an access element, it is essential to fabricate an access diode having good electric characteristics with a high production yield.
However, the nonvolatile semiconductor memory device having the first structure described above uses a polysilicon layer or amorphous silicon layer as a semiconductor layer forming an access diode, which leads to a wide range of variations in the electric characteristics of the access diode. The variations in the electric characteristics result from a great number of grains mainly present in these layers and prevent the access diode from fully functioning. Therefore, with the first structure, a nonvolatile semiconductor memory device with high performance is hardly realized.
The nonvolatile semiconductor memory device having the second structure described above uses a diffusion region formed in a semiconductor substrate that is a single-crystal silicon layer as a semiconductor layer forming an access diode, thereby resulting in its excellent electric characteristics. However, since the word line is formed in the diffusion region, it is difficult to pass a sufficient amount of current and to ensure a large S/N ratio. Therefore, with the second structure, a nonvolatile semiconductor memory device with high performance is hardly realized.
The nonvolatile semiconductor memory device having the third structure described above has a shot key diode formed as an access diode, which may be relatively excellent in its electric characteristics as compared with a pn junction diode. However, since the access diode includes a polysilicon layer, a wide range of variations still occurs in the electric characteristics. Therefore, with the third structure, nonvolatile semiconductor memory devices with high performance are hardly fabricated with a high production yield.
Therefore, it has been very difficult to manufacture nonvolatile semiconductor memory devices having reduced memory cell array areas and good characteristics with a high production yield, and the development of the technique that satisfies all of these conditions has been long waited.
An object of the present invention is to provide a high-performance miniaturized nonvolatile semiconductor memory device that can be manufactured inexpensively.
In accordance with one aspect of the present invention, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first conductive line, a second conductive line, and a memory cell. The semiconductor substrate has a main surface. The first conductive line is positioned above the main surface of the semiconductor substrate. The second conductive line is provided to intersect the first conductive line. The memory cell is positioned at or in proximity to a region where the first conductive line and the second conductive line intersect, and has one end electrically connected to the first conductive line and the other end electrically connected to the second conductive line. The memory cell includes a memory element and an access diode electrically connected in series. The access diode includes a semiconductor layer recrystallized by melting-recrystallization and has a pn junction inside the semiconductor layer.
In accordance with another aspect of the present invention, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first conductive line, a second conductive line, and a memory cell. The semiconductor substrate has a main surface. The first conductive line is positioned above the main surface of the semiconductor substrate. The second conductive line is provided to intersect the first conductive line. The memory cell is positioned at or in proximity to a region where the first conductive line and the second conductive line intersect, and has one end electrically connected to the first conductive line and the other end electrically connected to the second conductive line. The memory cell includes a memory element and an access diode electrically connected in series. The access diode has a first semiconductor layer selectively grown on the main surface of the semiconductor substrate by epitaxial growth and has a pn junction within the first semiconductor layer or at an interface between the first semiconductor layer and the semiconductor substrate.